GT PDBF Logic Synthesis Benchmark Suite

Purpose of the benchmark suite

This page provides reproducible PDBF synthesis problems in standard PLA format. The benchmark suite collects experimental families used across the GT paper series: Contextual RTL and open-source RTL candidate studies associated with Paper II, real-RTL legal-completion validation associated with Paper III, memory-oriented PDBF experiments associated with Paper IV, and large-input scalability experiments associated with Paper VI. Additional semantic and AI-inspired PDBF benchmarks are provided as supporting open synthesis challenges.

GT synthesis results are reported as simple two-input logic-gate count, maximum logic depth, and synthesis time. The present benchmark release provides the original PLA specifications and synthesis statistics. GT synthesized netlists are not included in this release.

AI-Inspired Contextual PDBF Benchmarks

These benchmarks are synthetic, reproducible AI-like decision and classification functions expressed directly as contextual PDBFs. They are intended to study combinational synthesis over strongly constrained quantized feature domains; they are not results extracted from trained neural-network models and should not be interpreted as AI-accuracy benchmarks.

The current table reports 29 evaluated examples for which both GT and ABC synthesis data are available. Input features are quantized and encoded so that only the listed care terms are admissible; all other nominal Boolean input combinations are contextual don't-cares. Results are reported as Gates|Levels. Multiple GT entries show alternative synthesized implementations and therefore expose gate/depth tradeoffs rather than a single selected operating point.

Railway Signal Anomaly synthesis results are included from the supplied result listing; PI, PO, care-term and care-density metadata are left unspecified here until read directly from the PLA header.

Care density is |C|/2^PI. Where several GT implementations are listed, the minimum gate count and minimum depth may occur in different variants. ABC columns correspond only to the evaluated synt and transtoch flows shown here. The spacecraft-autonomy testcase is not included in this table because it is presently being retained as a GT input-loader regression/debug case rather than as a synthesis result.

Paper II — Original Contextual RTL PDBF Demonstrations

These five benchmarks are the original RTL-derived demonstrations reported in Paper II and are distinct from the five open-source A/B/C candidate experiments shown later on this page. Extending Completion Optimization to RTL Designs Through Contextual Partially Defined Boolean Functions. Each row represents a Contextual PDBF extracted from an internal RTL block whose nominal local input space is much larger than the set of locally reachable care terms. The ABC result is for the evaluated fixed legal completion of the same Contextual PDBF, while the GT result is obtained by searching the Legal Completion Opportunity Space before circuit optimization. Results are reported as two-input gate count and maximum logic depth.

These are the five principal Paper II demonstrations. The comparison is intentionally framed as fixed Legal Completion + ABC synthesis versus GT search over the Legal Completion Opportunity Space; it is not presented as a general tool-to-tool comparison of ABC and GT.

Paper II — Controlled 15-Case RTL-Structured Validation

This 15-benchmark suite complements the five primary Paper II demonstrations with source-independent RTL-structured Contextual PDBFs. The cases are controlled synthesis experiments, not provenance-qualified projections of specific upstream RTL designs.

For each PDBF, conventional ABC optimization was evaluated after the unspecified terms had been fixed to zero using deepsyn, an independent transtoch run, and a chained deepsyn → transtoch flow. The table retains the Pareto-best ABC gate/depth points across those flows. GT instead searches the original Legal Completion Opportunity Space before circuit optimization.

Verification. Across the controlled suite, all 73 reported implementation artifacts (28 GT and 45 ABC) were exhaustively checked on every specified care assignment of the unchanged original PDBFs, with zero observed mismatches. All 45 ABC artifacts were also exhaustively evaluated on every omitted input assignment; every omitted assignment produced the all-zero output vector, independently confirming the zero-completion baseline.

Interpretation. Every benchmark has at least one reported GT point that Pareto-dominates the reported ABC Pareto set. This is not presented as a generic GT-versus-ABC comparison: it compares conventional optimization after contextual freedom has been fixed to zero with synthesis that retains and searches Legal Completion freedom.

Paper II — Open-Source RTL A/B/C Validation

This section reports the five current open-source RTL candidate experiments added to the Paper II evaluation. Each candidate is evaluated through three paths: A — source-derived RTL → Yosys → ABC, B — Contextual PDBF → fixed-zero Legal Completion → ABC, and C — Contextual PDBF → GT Legal Completion search. Structural results are reported as AIG AND nodes / AIG levels; multiple entries are retained Pareto points.

Interpretation. Flow A is the new Original-RTL structural baseline. Flow B is deliberately a fixed-zero Legal Completion and should not be treated as a proxy for the quality of the original RTL. Flow C retains the contextual don't-care freedom and searches Legal Completions before implementation optimization. Ibex, PicoRV32, DMA and AXIS contain GT points lower in both reported structural dimensions than their A points. OTP instead exposes a size/depth tradeoff: GT uses substantially fewer AIG AND nodes, while the shallowest Original-RTL point has lower depth.

Scope and provenance. These are candidate-level, source-derived/source-inspired contextual experiments, not automatic whole-design reachability or equivalence proofs. Ibex is evaluated under an explicit parameterization; PicoRV32 is a source-inspired execution-control abstraction; DMA is the corrected transfer-setup projection; OTP is a projected control relation over the supplied candidate context; and the submitted 96-care AXIS model is more restrictive than complete upstream arbitration behavior because source-permitted held-grant states are not all represented. Stronger upstream-source claims require regeneration from fixed source revisions with the relevant reachability constraints.

Metric. The A/B/C values are ABC AIG AND-node / AIG-level measurements. They are structural synthesis metrics and should not be interpreted directly as technology-mapped area, timing, power, routing or final physical PPA.

Paper III — Real-RTL Legal-Completion Validation

Paper III, GT AND Sequential Synthesis: Native Sequential Device PDBFs and Completion Optimization, adds a controlled five-candidate experiment over independently sourced RTL control logic. Each candidate was validated on its complete published care domain, then evaluated through three paths: source-derived RTL through Yosys/ABC, the same Contextual PDBF after fixed zero completion through ABC, and GT search over legal completions. Results below are Pareto points reported as Gates / Levels.

Result. For every candidate, at least one validated GT implementation strictly Pareto-dominates every available conventional RTL → ABC Pareto point in both gate count and maximum logic depth. Ibex, AXI and PicoRV32 also show coincident RTL → ABC and zero-completion → ABC fronts. DMA and ROM provide the stronger control: source-derived RTL → ABC is better than zero-completed Contextual PDBF → ABC, yet legal-completion search still produces a dominating GT point.

Interpretation. This experiment is not a generic GT-versus-ABC tool comparison. It isolates completion freedom: conventional synthesis optimizes a fixed implementation or fixed zero completion, whereas GT retains and searches the legal unspecified region before circuit optimization.

Paper III manuscript

Paper IV — Memory-Oriented / FSM PDBF Synthesis Results

These memory-oriented and FSM-style PDBF benchmarks are associated with the Paper IV evaluation family. They provide direct ABC/GT comparison where an ABC result is available, together with multiple GT netlist variants when they were obtained.

The first line of each benchmark section identifies the benchmark and gives PI, PO, Cubes, the available ABC result, the first GT result, and the PLA download link. Additional lines show alternative GT netlist variants for the same PDBF.

Semantic PDBF synthesis results with available ABC comparisons

These semantic benchmarks provide direct ABC/GT comparison where an ABC result is available, together with multiple GT netlist variants when they were obtained.

The first line of each benchmark section identifies the benchmark and gives PI, PO, Cubes, the available ABC result, the first GT result, and the PLA download link. Additional lines show alternative GT netlist variants for the same PDBF.

Medium-input semantic PDBF benchmarks

In this benchmark suite, examples with hundreds to several thousand primary inputs are classified as medium-input PDBFs. The cases below model networking, security, storage, telecommunications and policy/control hardware.

The PLA files should be uploaded using exactly the benchmark filenames shown in the first column.

Contextual PDBF synthesis: blockwise and whole-design examples

These three examples compare contextual PDBF synthesis at the block and whole-design levels across arithmetic, sequential/control, and instruction-decoding structures. For each example, the component blocks are synthesized using their specified contextual care domains, and the complete design is shown both as a blockwise assembled implementation and as a directly synthesized whole contextual PDBF.

The Design column identifies the individual contextual block or the corresponding whole-design case. Where multiple ABC or GT synthesis variants are available, they are shown on additional lines for the same design.

“Whole — Assembled” denotes the complete function corresponding to the interconnected block implementation; “Whole — Contextual” denotes direct synthesis of the corresponding externally specified whole-design PDBF. Cube counts describe specified PLA care terms.

Randomly generated PDBFs: cube quantity to netlist parameters comparison

This experiment keeps the benchmark size fixed at 250 primary inputs and 1 primary output while increasing the number of PDBF cubes from 16 to 2,000. The table compares the resulting ABC and GT netlist gate counts and logic levels.

Each PLA button links to /benchmarks/<Benchmark>.pla.

Paper VI — PDBF Input-Scalability Challenge

This Paper VI benchmark series studies PDBF synthesis as the primary-input dimension grows from hundreds to tens of thousands, hundreds of thousands and one million inputs.

The results illustrate that primary-input count alone does not determine synthesis difficulty. The care structure, number of outputs, cube structure and interactions among conditions can be equally important.

Reported synthesis metrics

PI — number of primary inputs. PO — number of primary outputs. Cubes — number of PLA product terms.

For the GT results, Gates denotes the number of internal two-input simple/AIG logic nodes. Complemented AIG edges do not count as additional gates. Levels is the maximum logic depth from a primary input to a primary output.

GT Time is the reported synthesis runtime in seconds for the corresponding experiment.

Verification rules and acceptance criteria

A synthesized network is a valid implementation of a benchmark only if it satisfies every specified PDBF output value over the complete care domain of the PLA.

1. For every PLA cube and every output specified as 0, the synthesized output must be 0 for every concrete binary input assignment covered by that cube.
2. For every PLA cube and every output specified as 1, the synthesized output must be 1 for every concrete binary input assignment covered by that cube.
3. An output value - is unrestricted. A term for which all outputs are - imposes no PDBF constraint and should not be included in the effective truth table.
4. Verification must cover the complete input region represented by a cube, not only one representative minterm. If a PLA input is - and belongs to the effective support of the synthesized output, all relevant assignments of that free support variable must be checked or proven equivalent.
5. If all primary inputs in the effective support of an output are fixed within a PLA cube, evaluation of that support assignment proves the output over the complete cube; primary inputs outside the output support cannot affect the result.
6. Two overlapping cubes may not impose contradictory values on the same output. If two terms require opposite values, 0/1 or 1/0, for an output, their input cubes must be disjoint. Therefore at least one input position must contain an explicit complementary pair 0/1 or 1/0.
7. Behavior outside the PDBF care domain is unrestricted. Two valid synthesized networks do not have to be globally equivalent if they make different choices in don't-care regions.

Results obtained with other synthesis tools

We welcome independent experiments with these benchmarks. If you obtain a synthesis result using another combinational logic synthesis tool, please inform us of the result and the synthesis conditions.

For meaningful comparison, please identify the tool and version, synthesis commands/options, hardware platform, runtime, peak memory if available, gate/node count and logic depth. The resulting implementation can be validated against the original PLA using the verification criteria above.

A valid result with fewer gates, fewer levels, or competitive synthesis time is welcome.

Input-size terminology used in this suite

The terms below are benchmark-suite classifications rather than claims of universal EDA terminology: